The present invention relates to electronic circuits, and more particularly, to loop circuits that reduce bandwidth variations.
A phase-locked loop (PLL) is an electronic circuit that generates one or more periodic (clock) output signals. A PLL adjusts the frequency of a feedback signal from the output of an oscillator to match in phase the frequency of an input reference clock signal. Phase-locked loops (PLLs) are an essential building block of many integrated circuits, providing periodic signals for data recovery, data transfer, and other clocking functions. PLLs often supply a clock signal to one or more counters or dividers that divide a signal from the oscillator to a lower frequency clock signal for distribution around an integrated circuit or system.
The noise performance of a PLL depends in part on the design of the individual components in the PLL. The noise performance of a PLL also depends heavily on the loop bandwidth. The loop bandwidth of a typical PLL is sensitive to variations in temperature, process, and the power supply voltage. For example, variations in temperature can cause the noise performance of a PLL to degrade dramatically.
Many modern PLLs are required to operate within an industrial temperature range. An industrial temperature range is typically a wide temperature range, e.g., −40° C. to 125° C. Wide temperature variations can cause an even larger degradation in the noise performance of a PLL.